In certain types of data processing applications, such as emulators and development systems, it is very important to be able to track the course of execution of instructions by the data processor. In many data processors, the internal status of the processor can be determined by monitoring and interpreting the various output signals provided by the processor in the normal course of operation. On the other hand, some events, such as instruction tracing or interrupt exceptions, are difficult to track from outside the processor. In some processors in which some important events are not otherwise externally discernable, special output signals are provided whenever such an event occurs, with each output signal indicating a given type of event. In other processors, internal logic is provided to monitor the status of the processor and to provide an encoded set of "status" signals which indicate the internal status of the processor. An example of such encoding logic is set forth in U.S. Pat. No. 4,270,167 wherein three (3) output signals (S2, S1 and S0) are suitably encoded to indicate the various relevant states of the processor.
In certain processors, such as one having an internal instruction queue or pipeline, the interactions of the processor with the queue or pipeline are not readily discernable from outside the processor. In such systems, these events are made externally "visible" by special logic which monitors such activities, and provides a set of "status" signals which indicate when the monitored events occur. An example of such logic is also set forth in U.S. Pat. No. 4,270,167 wherein two (2) output signals (QS1 and QS0) are suitably encoded to indicate the various relevant queue activities.
In systems having instruction or data caches which are tightly coupled to the processor, the interactions between the processor and the cache(s) may also not be readily discernible to external devices. However, in software or hardware development or emulation systems, it is critical to be able to track the activities of the processor as it processes the instructions and data as they flow into and out of the caches.
In general, providing non-encoded status signals requires as many distinct output signals as there are monitored status conditions. Even encoding the status conditions requires a sufficient number of distinct output signals to accommodate the encoding scheme. Since the number of output signals available for use by integrated circuit processors is very limited, a mechanism for indicating the current status of a plurality of different operating conditions using a minimum of distinct output signals is desirable.